U.S. Pat. No. 6,979,884 (“the '884 patent”), which issued on Dec. 27, 2005, discloses techniques for fabricating bipolar transistor structures. FIG. 1 shows a partial bipolar transistor structure 100 disclosed in the '884 patent. The FIG. 1 partial bipolar transistor structure 100 includes a silicon-containing substrate 102 having isolation regions 104, e.g. trench isolation or field oxide isolation, formed therein. The substrate 102 also includes a collector region 108 and a collector contact region 106. A patterned protective material, such as oxide or nitride or oxynitride, is formed on top of selected portions of the device area. The structure 100 also includes a base region that comprises intrinsic base portion 112 and surrounding extrinsic base layer 114. The intrinsic base 112 comprises silicon (Si) or germanium (Ge) or a combination of silicon and germanium. The intrinsic base 112 is typically monocrystalline, while the extrinsic base 114 is typically polycrystalline silicon or SiGe. An emitter opening 118 is formed within a dielectric (e.g. oxide) layer 116 and raised extrinsic base 114. Within the emitter opening 118 is an oxide layer 120 and annular insulating spacer 122. The insulating spacer 122 is typically referred to as an “inside” spacer because it is formed within the opening 118 in the dielectric layer 116. The inside spacer 122 is a dielectric such as oxide or nitride. As shown in FIG. 1, the dielectric layer 116 and the underlying extrinsic base layer 114 form a raised extrinsic base/dielectric stack.
Those skilled in the art will appreciate that the inside spacer 122 is utilized to define the final dimension of the emitter of the bipolar transistor structure and to provide lateral emitter-base isolation. Those skilled in the art will also appreciate that, as device sizes become smaller (e.g., 0.18 μm processes), thus reducing the size of the emitter window, the ability to utilize inside spacers to define the emitter dimension and to obtain adequate emitter-base isolation becomes increasingly problematic.
There is an increasing desirability in the electronics industry, particularly with respect to handheld, wireless devices, for the use of integrated circuits that combine the high speed, high gain advantages of bipolar transistor technology with the simple, low power logic associated with CMOS technology. While circuit designers recognize the advantages of this so-called “BiCMOS” technology, the very high level of integration that can be achieved with CMOS technology still cannot be realized with BiCMOS technology. Thus, it is highly desirable to reduce the size of bipolar devices.
Circuit designers are relying on self-aligned bipolar architectures to achieve the narrower emitters and more critical extrinsic/intrinsic base alignments necessary for reduced bipolar device size. Many of these bipolar architectures achieve self-alignment through the use of sacrificial emitters.
U.S. Pat. No. 6,869,853 (“the '853 patent”), which issued on Mar. 22, 2005, discloses techniques for fabricating a bipolar transistor structure using a sacrificial emitter.
FIGS. 2A-2E show a sequence of steps for fabricating a bipolar structure using the sacrificial emitter techniques of the '853 patent. As shown in FIG. 2A, isolation structures 202, such as shallow trench isolation (STI) silicon dioxide, are formed in an amorphous silicon layer 201. A polycrystalline silicon-germanium layer 204 and a silicon or silicon-germanium layer 203 are formed on isolation structures 202 and silicon layer 201, respectively, by epitaxial growth. The portion of the layer 203 that will be under a subsequently formed emitter is referred to as an “intrinsic base region”, while the remainder of the layer 203 and the poly-SiGe layer 204 as “extrinsic base regions.” As shown in FIG. 2B, an oxide layer 213, e.g. silicon dioxide, is then formed and a polycrystalline silicon layer 211 is formed over the oxide layer 213. Polycrystalline silicon layer 211 serves as the sacrificial emitter material, and therefore does not require an implantation step or an activation step. As further shown in FIG. 2B, a photoresist (PR) sacrificial emitter mask 241 is patterned on the polysilicon layer 211 for use in defining the sacrificial emitter. As shown in FIG. 2C, the patterned photoresist mask 241 is then used to etch the polysilicon layer 211 to form the sacrificial emitter 211′. Spacers 212, e.g. silicon nitride, are then formed on the outside sidewalls of the sacrificial emitter 211′, as shown in FIG. 2D. Portions of the oxide layer 213 that are not under the sacrificial emitter 211′ and the sidewall spacers 212 are then removed and an extrinsic base implant step is performed, as shown in FIG. 2E. As can be appreciated by reference to FIG. 2E, the extrinsic base implant step is self-aligned with respect to the spacers 212. As shown in FIG. 2F, a layer of conformal oxide 221 is then formed over the FIG. 2E structure and etched back to expose the polysilicon sacrificial emitter 211′. The sacrificial emitter 211′ is then removed, as shown in FIG. 2G, using a poly-etch process that is selective to the sidewall spacers 212 and to oxide layers 221 and 213. A portion of the oxide layer 213 is then removed to expose a portion of layer 203. A layer of emitter material, e.g. polysilicon, is then formed, doped, activated and etched to form polysilicon emitter 231 of the bipolar transistor structure, as shown in FIG. 2H.
Those skilled in the art will appreciate that a sacrificial emitter process of the type described above involves the deposition and etch back of multiple layers of polysilicon and dielectrics. This inevitably results in some residues being left behind in each such operation, potentially resulting in operational degredation and, thus, yield loss. Furthermore, as the critical dimensions in these bipolar devices decrease, the tradeoffs in the lightly doped extrinsic base implant and the need to minimize extrinsic base to collector capacitance become more problematic.
U.S. Pat. No. 7,026,666 (“the '666 patent”), which issued on Apr. 11, 2006, shows another self-aligned technique for fabricating a bipolar transistor structure.
Referring to FIG. 3A, the technique disclosed in the '666 patent includes the formation of a structure that comprises a p-type silicon substrate 302 having an n-type collector region 304 and a p-type Si, SiGe or SiGe:C epitaxial layer 306. The epitaxial layer 306 is deposited over the surface of the substrate 302 such that a mono crystalline portion 308 of the epitaxial layer 306 is deposited over a mono crystalline portion 310 of the substrate 302 and a poly crystalline portion 312 of the epitaxial layer 306 is deposited over isolation oxide 314. An ONO stack 316 comprising thin silicon dioxide layer 318, silicon nitride layer 320 and top silicon dioxide layer 322, is formed on the substrate 302.
Referring to FIG. 3B, an emitter mask layer (not shown) is then formed over the top oxide layer 322 and utilized to selectively etch the top oxide layer 322 and the nitride layer 320 to form an emitter window 324; the thin oxide layer 318 is left in place as an etch stop. A self-aligned collector implant is then performed through the emitter window 324. The thin oxide layer 318 is then etched to expose a portion of the epi portion 308 and a layer of polysilicon 328 is formed over the structure. The polysilicon layer 328 may be in-situ doped with n-type dopant while deposited by low pressure chemical vapor deposition (LPCVD). A polysilicon emitter 330 is then formed by etching back the polysilicon layer 328 such that the top surface of the poly emitter 330 is coplanar with the top surface of the top oxide layer 322, as shown in FIG. 3C. The poly emitter 330 is then exposed by selectively removing the top oxide layer 322, resulting in the structure shown in FIG. 3D.
Referring to FIG. 3E, nitride spacers 132 are then formed on the exposed sidewalls of the poly emitter 330 by depositing a layer 324 of silicon nitride and anisotropically etching the nitride layer 324. As shown in FIG. 3F, the thin oxide layer 318 is then removed and a heavily doped epitaxial layer 340 is selectively deposited over the base epitaxial region 306 and over the poly emitter 330. Referring to FIG. 3G, the thickness of the nitride spacer 332 is then increased forming and etching nitride layer 350 to provide thicker spacers 350, thereby increasing the width of the emitter region 342 in order to prevent the emitter silicide layer from shorting with the base silicide and in order to prevent the emitter contact etch from exposing the base region 344.
FIG. 3H shows the formation of a silicide layer 354 at the surface of the raised extrinsic base region 344 and at the top surface of the emitter region 342. Those skilled in the art will appreciate that the emitter structure is completed by forming an emitter contact to the silicided upper surface 354 of the emitter region 342.